Setting bits (masked or), Testing bits (tm and tcm), Setting bits (masked or) testing bits (tm and tcm) – Zilog Z16F2810 User Manual
Page 54: Figure 9, Masked logic example: clearing a bit, This leaves the value, Zneo, Cpu core user manual, Example, Bit 0
Operand Addressing
UM018809-0611
38
ZNEO
®
CPU Core
User Manual
This leaves the value
FFFF_FF50H
in register R15. Figure 9 displays how this example
clears only one bit of register R15.
Setting Bits (Masked OR)
The logical OR instruction stores a 0 bit only if the corresponding bit is clear in both the
source and destination. In effect, if the source (mask) bit is 1, the destination bit is set. If
the mask bit is 0, the destination bit is not changed.
Example.
The following assembly language statements initialize register R15 and then set
bits [2,1] of that register:
LD R15, #00000070H ; LSB = 0111_0000B
OR R15, #00000006H ; Set R15 bits 1 and 2
This leaves the value
0000_0076H
(LSB =
0111_0110B
) in register R15.
Testing Bits (TM and TCM)
The TM instruction performs an internal AND to test mask-selected bits in the destination
register, but does not changes the source or destination register contents. Instead, TM sets
the
Z
flag if the tested destination bits are all 0.
To select a bit to test, set the corresponding bit in the source (mask) operand as given in
the example below.
Example.
The following assembly language statements initialize register R15 and then
test bit 2 of that register:
LD R15, #00000070H ; LSB = 0111_0000B
TM R15, #00000004H ; Test bit 2
JP Z, BIT_IS_CLEAR
Figure 9. Masked Logic Example: Clearing a Bit
0
1
1
1
0
0
0
0
R15[7:0] = 70H
1
1
0
1
1
1
1
1
MASK = FFFF_FFDFH
0
1
0
1
0
0
0
0
R15[7:0] = 50H
Bit
5
Bit
32
AND R15, #FFFFFFDFH
; Clear Bit 5 of Register 15
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Bit
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