Software traps – Zilog Z16F2810 User Manual
Page 69
UM018809-0611
Software Traps
ZNEO
®
CPU Core
User Manual
53
Software Traps
The TRAP Vector instruction allows software to invoke any vectored service routine, par-
ticularly software-defined traps. The TRAP instruction executes the pointed service rou-
tine by the specified vector. Software traps use the same vector space as system exceptions
and interrupts. Like other vectors, the 32-bit trap vector value is stored in a memory quad.
Possible vectors are numbered from 0 to 255 (
0H
to
FFH
). The possible vector space
includes memory quads
0000_0000H
to
0000_03FCH
. Each vector quad’s physical
address is 4
Vector.
Example.
The following instruction executes a software-defined service routine pointed
to by Vector 255 stored in quad
0000_03FCH
:
TRAP #FFH
A software trap service routine must execute an IRET instruction to return from the trap.
Other vectors not used by the CPU or peripherals are available for software-defined traps.
For example, Vector 255 (vector quad
0000_03FCH
) is initialized with a pointer to a user-
input error handling routine, which is then invoked by a
TRAP
FFH
instruction.
For a list of vectors used by the CPU and internal peripherals, refer to the ZNEO product
specification that is specific to your device .
A TRAP instruction is used with exception or interrupt vectors but the TRAP instruction
does not sets any register bits in I/O memory that the corresponding service routine is
likely to inspect. For more information, see the
Some locations in the vector space may be reserved by the CPU for other uses. For exam-
ple, a typical ZNEO CPU uses the memory quad at
0000_0000H
for option bits; there-
fore, Vector 00 is not available for service routines. Software can use the instruction
TRAP
#01
to invoke the RESET vector at
0000_0004H
. For more information, see the
Note: