Zilog Z16F2810 - Manual (Page 58)

Interrupts UM018809-0611
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ZNEO
®
CPU Core
User Manual
Master Interrupt Enable flag ( IRQE ) in the FLAGS register in I/O memory. It is possible to
enable or disable interrupts by writing to the Flags Register directly. You can enable or
disable the individual interrupts using control registers in the Interrupt Controller.
For information about the Interrupt Controller, refer to the ZNEO Product Specification
that is specific to your device.
Interrupt Processing
When an enabled interrupt occurs, the ZNEO CPU performs the following tasks to pass
control to the corresponding interrupt service routine:
1. Push the Flags Register, including the Master Interrupt Enable bit ( IRQE ), onto the
stack.
2. Push 00H (so SP alignment is not changed).
3. Push PC[7:0] (Program Counter bits [7:0]) onto the stack.
4. Copy the state of the IRQE flag into the Chained Interrupt Enable flag ( CIRQE ).
5. Push PC[15:8] onto the stack.
6. Push PC[23:16] onto the stack.
7. Push PC[31:24] onto the stack.
8. Disable interrupts (clear IRQE ).
9. Fetch interrupt vector bits [31:24] into PC[31:24].
10. Fetch interrupt vector bits [23:16] into PC[23:16].
11. Fetch interrupt vector bits [15:8] into PC[15:8].
12. Fetch interrupt vector bits [7:0] into PC[7:0].
13. Begin execution at the new Program Counter address specified by the Interrupt Vector.

Figure 10 displays the effect of vectored interrupts on the Stack Pointer and the contents of
the stack.
Note: