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Interrupt priority and nesting – Zilog Z16F2810 User Manual

Page 61

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UM018809-0611

Interrupts

ZNEO

®

CPU Core

User Manual

45

6. Pop the Flags register, including the Master Interrupt Enable bit (

IRQE

), from the

stack. This returns the

IRQE

bit to its state before the interrupt occurred (assuming the

contents of the stack are not altered by the interrupt service routine).

7. Begin execution at the new Program Counter address.

If the

CIRQE

flag is 1 and one or more vectored interrupts are pending, executing the IRET

instruction results in the following operation:

1. Disable interrupts (clear the IRQE flag).

2. Load the Program Counter directly from the vector table quad for the highest-priority

pending interrupt.

3. Begin execution at the new Program Counter address.

This chained-interrupt optimization omits unneeded pop and push cycles when program
control passes directly from one interrupt service routine to another.

Whenever a vectored interrupt or system exception occurs, the previous state of the

IRQE

flag is copied to the

CIRQE

flag after the Flags Register is pushed onto the stack. As a

result, interrupt chaining is disabled if interrupts are globally disabled (

IRQE=0

) when a

nonmaskable interrupt or system exception occurs.

Programs that branch to interrupt service routines directly—for example, by executing a
PUSHF followed by a CALL—must set or clear the

CIRQE

flag to enable or disable in-

terrupt chaining, respectively. Otherwise, the IRET that ends the routine might chain to
another interrupt unexpectedly.

The following assembly language statements clear the

CIRQE

flag:

LD.UB R5, FLAGS ;Read the current FLAGS value

AND R5, #11111101B ;Clear bit 1 (CIRQE)

LD.B FLAGS, R5 ;Write back with CIRQE flag cleared

Interrupt Priority and Nesting

The Interrupt Controller assigns a specific priority to each IRQ signal. When two IRQ sig-
nals are asserted at the same time, the higher priority interrupt service routine is executed
first. An interrupt service routine enables the vectored interrupt nesting, which allows
higher priority requests to interrupt the request being serviced.

Observe the following steps during the interrupt service routine to enable vectored inter-
rupt nesting:

1. Push the current value of the Interrupt Enable Registers in I/O memory onto the stack.

Caution:

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