Zilog Z16F2810 - Manual (Page 73)

UM018809-0611 Instruction Opcodes
ZNEO
®
CPU Core
User Manual
57
0000 0000 0010 dddd
0xrr rrrr rrrr rrrr
LD Rd, soff14(PC) Load Quad pointed to by program counter plus
14-bit signed offset.
0000 0000 0010 dddd
1xrr rrrr rrrr rrrr
LEA Rd, soff14(PC) Load register with PC-based effective address.
0000 0000 0011 dddd
zbrr rrrr rrrr rrrr
LD.UB Rd, soff14(PC)
LD.SB Rd, soff14(PC)
LD.UW Rd, soff14(PC)
LD.SW Rd, soff14(PC) Load memory Byte or Word pointed to by pro-
gram counter plus 14-bit signed offset with
Unsigned/Signed extension.
0000 0000 01xx xxxx — Unimplemented
0000 0000 1xxx xxxx — Unimplemented
0000 0001 cccc dddd LD cc, Rd Load register with condition code.
0000 0010 xxxx xxxx — Unimplemented
0000 0011 00bz dddd
aaaa aaaa aaaa aaaa
LD.UB Rd, addr16
LD.SB Rd, addr16
LD.UW Rd, addr16
LD.SW Rd, addr16 Load memory Byte or Word with Unsigned/
Signed extension; 16-bit address.
0000 0011 0100 dddd
aaaa aaaa aaaa aaaa
LD Rd, addr16 Load memory Quad; 16-bit address.
0000 0011 0101 ssss
aaaa aaaa aaaa aaaa
LD.B addr16, Rs Store memory Byte; 16-bit address.
0000 0011 0110 ssss
aaaa aaaa aaaa aaaa
LD.W addr16, Rs Store memory Word; 16-bit address.
0000 0011 0111 ssss
aaaa aaaa aaaa aaaa
LD addr16, Rs Store memory Quad; 16-bit address.
0000 0011 10bz dddd
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD.UB Rd, addr32
LD.SB Rd, addr32
LD.UW Rd, addr32
LD.SW Rd, addr32 Load memory Byte or Word with Unsigned/
Signed extension; 32-bit address.
0000 0011 1100 dddd
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD Rd, addr32 Load memory Quad; 32-bit address.
0000 0011 1101 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD.B addr32, Rs Store memory Byte; 32-bit address.
0000 0011 1110 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD.W addr32, Rs Store memory Word; 32-bit address.
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description