Zilog Z16F2810 - Manual (Page 44)

Operand Addressing UM018809-0611
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ZNEO
®
CPU Core
User Manual
Immediate Data
An Immediate Data operand specifies a source value to be used directly by the instruction.
Example. The assembly language statement below loads ALU Register R7 with the value
42H :
LD R7, #42H
The hash mark prefix (#) on the second (source) operand indicates to the assembler that
the value is Immediate Data, so this example loads the R7 register with the value
42H .
Immediate data is stored as part of the instruction opcode. Depending on the opcode, an
immediate data value can be of the same size as the destination (8, 16 or 32 bits), or it may
contain fewer bits to shorten the opcode.
A destination-sized immediate operand (imm syntax symbol) is used directly by the opera-
tion. A shorter immediate operand must be considered signed (simm) or unsigned (uimm).
A signed immediate value is sign-extended to the destination size before it is used. An
unsigned immediate operand is zero-extended to the destination size before it is used. For
more information, see the
Memory Data Size section on page 30 and the Resizing Data
section on page 31.
An immediate value does not address data memory, so it cannot be used as the destination
operand. Immediate data is read by the Fetch Unit, so it is not affected by the constraints
described in the
I/O Memory Precautions section on page 18.
Register Addressing
A Register operand specifies a 32-bit Arithmetic and Logic Unit (ALU) register to be used
with the instruction. ALU registers are the CPU’s high-speed work space, much faster than
ordinary internal or external memory. There are 16 ALU registers, named R0 to R15. See
the
ALU Registers section on page 4 for details.
As mentioned previously, the following assembly language statement loads the destination
register, R7, with data from the source register, R8:
LD R7, R8
Depending on the instruction, a register name can be used for either the source or destina-
tion operand, or both. Each register is 32-bits (four bytes) wide, and all 32 bits of a register
are used unless the register’s value is loaded into an 8-bit or 16-bit memory location.
The ZNEO CPU assembler recognizes FP as a synonym for R14 and SP as a synonym for
R15. For details, see the
Using the Frame Pointer (R14) section on page 37 and the Using
the Stack Pointer (R15) section on page 36. The UDIV64 instruction uses a 64-bit RRd
register pair operand that employs two 32-bit ALU registers. See the UDIV64 section on
page 182 for details.