Zilog Z16F2810 - Manual (Page 55)

UM018809-0611 Operand Addressing
ZNEO
®
CPU Core
User Manual
39
This leaves R15 unchanged, but sets the Z flag as R15[2] is clear.
The TCM instruction (Test Complement under Mask, discussed on page 172 ) comple-
ments the destination value before ANDing it to the mask. In effect, TCM is identical to
TM except it sets the
Z flag if the tested destination bits are all 1.
Example . The following assembly language statements initialize register R15 and then
test bits [2,1] of that register:
LD R15, #00000070H ; LSB = 0111_0000B
TCM R15, #00000006H ; Test bits 1 and 2
JP Z, BITS_ARE_ONES
As a result, R15 remains unchanged but clears the Z flag because neither bit R15[2,1] is 1.
Jump Addressing
The ZNEO CPU jump instructions (JP and CALL), are used to alter the program flow.
These instructions alter the Program Counter, which indicates the next instruction to be
fetched. A few considerations are listed below.
•
All instructions must begin on an even address.
•
Instruction fetches bypass the internal I/O space. The result of an instruction fetch is
not defined in the range
FFFF_E000H – FFFF_FFFFH ( FF_E000H – FF_FFFFH on
devices that ignore address bits [31:24]).
•
A small device-specific address block starting at 0000_0000H is reserved for CPU
option bits and interrupt, trap, or exception vectors.
For details about option bits and vectors, refer to the ZNEO product specification that is
specific to your device .
Assembly language statements use a label, expression, or numeric value to indicate the 32-
bit jump destination. The ZNEO CPU assembler analyzes the address and determines the
best address mode to use in the assembled object code.
In object code, following two jump address modes are available:
Direct Address. The JP, JP cc, or CALL opcode includes four operand bytes containing
the 32-bit jump destination address. The destination address is written directly to the Pro-
gram Counter to indicate the next instruction. Bit [0] of the operand is ignored.
Note: