Altera RapidIO II MegaCore Function User Manual
Page 96

4–54
Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function
August 2014
Altera Corporation
User Guide
Table 4–29
lists the fields of the gen_rx_hd_data bus.
Table 4–29. RapidIO Header Fields in gen_rx_hd_data Bus
Field
gen_rx_hd_data Bits
Value
Comment
pd_size[8:0]
[114:106]
Size of payload data, in bytes.
VC
[105]
0
The RapidIO II IP core supports only VC0.
CRF
[104]
prio[1:0]
[103:102]
tt[1:0]
[101:100]
ftype[3:0]
[99:96]
destinationID[15:0]
[95:80]
For packets with an 8-bit device ID, bits [95:88] (bits
[15:8] of the destinationID) are set to 8’h00.
sourceID[15:0]
[79:64]
When ftype[3:0] has the value of 7, this field is used
as the tgtDestinationID field.
For packets with an 8-bit device ID, bits [79:72] (bits
[15:8] of the sourceID) are set to 8’h00.
specific_header[63:0]
[63:0]
Fields depend on the format type specified in ftype.
Refer to
Table 4–30
.
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- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
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- Floating-Point (157 pages)
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- LVDS SERDES Transmitter / Receiver (72 pages)
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- RAM Initializer (36 pages)
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- DCFIFO (28 pages)