Altera RapidIO II MegaCore Function - Manual (Page 14)

1–6 Chapter 1: About The RapidIO II MegaCore Function
IP Core Verification
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Constrained random techniques generate appropriate stimulus for the functional
verification of the IP core. Functional and code coverage metrics measure the quality
of the random stimulus, and ensure that all important features are verified.
Hardware Testing
Altera tests and verifies the RapidIO II IP core in hardware for different platforms and
environments.
The hardware tests cover serial 1x, 2x, and 4x variations running at 1.25, 2.5, 3.125, 5.0,
and 6.25 Gbaud, and processing the following traffic types:
■ NREAD s of various payload sizes
■ NWRITE s of various payload sizes
■ NWRITE_R s of various payload sizes
■ SWRITE s of various payload sizes
■ Port-writes
■ DOORBELL messages
■ MAINTENANCE reads and writes
The hardware tests also cover the following control symbol types:
■ Status
■ Packet-accepted
■ Packet-retry
■ Packet-not-accepted
■ Start-of-packet
■ End-of-packet
■ Link-request, Link-response
■ Stomp
■ Restart-from-retry
■ Multicast-event
Interoperability Testing
Altera performs interoperability tests on the RapidIO II IP core, which certify that the
RapidIO II IP core is compatible with third-party RapidIO devices.
Altera performs interoperability testing with processors and switches from various
manufacturers including:
■ Texas Instruments Incorporated
■ Integrated Device Technology, Inc. (IDT)
Altera has performed interoperability tests with the IDT CPS-1848 and IDT CPS-1616
switches. Testing of additional devices is an on-going process.