Altera RapidIO II MegaCore Function - Manual (Page 9)

August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
1. About The RapidIO II
MegaCore Function
The RapidIO interconnect—an open standard developed by the RapidIO Trade
Association—is a high-performance packet-switched interconnect technology
designed to pass data and control information between microprocessors, digital signal
processors (DSPs), communications and network processors, system memories, and
peripheral devices.
The Altera ® RapidIO II MegaCore ® function complies with the RapidIO v2.2
specification and targets high-performance, multi-computing, high-bandwidth, and
co-processing I/O applications.
Figure 1–1 shows an example system
implementation.
Features
This section outlines the features and supported transactions of the RapidIO II IP core.
Figure 1–1. Typical RapidIO Application
DSP
ASSP
DSP
ASSP
CPU
Memor
y
Memor
y
Memor
y
Memor
y
DSP
Interf
ace
Br
idge
FPGA
Controller Proprietary,
CPRI, OBSAI,
Ethernet, etc,
RapidIO II
MegaCore
Function
DSP
ASSP
RapidIO
Switch
System Interconnect