Altera RapidIO II MegaCore Function - Manual (Page 35)

Chapter 3: Parameter Settings 3–5
Capability Registers Settings
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
If the Doorbell module and the I/O slave module are both enabled, the Prevent
doorbell messages from passing write transactions
parameter is available. This
parameter controls support for preserving transaction order between DOORBELL
messages and I/O write request transactions sent to the IP core by user logic.
For more information about the Doorbell module, refer to “Doorbell Module” on
page 4–44 .
I/O Master Configuration
The I/O Master module settings specify properties of the I/O Logical layer
Avalon-MM Master module.
If you turn on Enable I/O Logical layer Master module, an I/O Master module is
configured in your RapidIO II IP core.
If the I/O Logical layer Master module is enabled, the Number of Rx address
translation windows
parameter is available. This parameter allows you to specify a
value from 1 to 16 to define the number of receive address translation windows the
I/O Master Logical layer supports.
For more information about the I/O Master receive address translation windows,
refer to
“Defining the Input/Output Avalon-MM Master Address Mapping
Windows” on page 4–11 .
I/O Slave Configuration
The I/O Slave module settings specify properties of the I/O Logical layer Avalon-MM
Slave module.
If you turn on Enable I/O Logical layer Slave module, an I/O Slave module is
configured in your RapidIO II IP core. Turning on this parameter makes the following
I/O Slave module parameters available in the parameter editor:
■ Number of Tx address translation windows allows you to specify a value from 1
to 16 to define the number of transmit address translation windows the I/O Slave
Logical layer supports.
For more information about the I/O Slave transmit address translation windows,
refer to
“Defining the Input/Output Avalon-MM Slave Address Mapping
Windows” on page 4–22 .
■ I/O Slave address bus width currently supports widths between 10 and 32 bits,
inclusive.
Capability Registers Settings
The Capability Registers tab lets you set values for some of the capability registers
(CARs), which exist in every RapidIO processing element and allow an external
processing element to determine the endpoint’s capabilities through MAINTENANCE
read operations. All CARs are 32 bits wide.