Altera RapidIO II MegaCore Function Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for RapidIO II MegaCore Function Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 218 |
| Size: | 3.02 MB |
Show table of contents
Document Outline
- RapidIO II MegaCore Function v14.0 and v14.0 Arria 10 Edition User Guide
- Contents
- 1. About The RapidIO II MegaCore Function
- 2. Getting Started
- Customizing and Generating IP Cores
- IFiles Generated for Altera IP Cores (Legacy Parameter Editor)
- IFiles Generated for Altera IP Cores by Qsys (Legacy Parameter Editor)
- Files Generated for Altera IP Cores
- Simulating IP Cores
- Integrating Your IP Core in Your Design
- Compiling the Full Design and Programming the FPGA
- Instantiating Multiple RapidIO II IP Cores
- 3. Parameter Settings
- Physical Layer Settings
- Transport Layer Settings
- Logical Layer Settings
- Capability Registers Settings
- Command and Status Registers Settings
- Error Management Registers Settings
- 4. Functional Description
- Interfaces
- Clocking and Reset Structure
- Logical Layer Interfaces
- Register Access Interface
- Input/Output Logical Layer Modules
- Input/Output Avalon-MM Master Module
- RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions
- Input/Output Avalon-MM Master Module Timing Diagrams
- Input/Output Avalon-MM Slave Module
- Initiating Read and Write Transactions
- Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets
- Input/Output Avalon-MM Slave Module Timing Diagrams
- Maintenance Module
- Doorbell Module
- Avalon-ST Pass-Through Interface
- Transport Layer
- Physical Layer
- Error Detection and Management
- 5. Signals
- 6. Software Interface
- Memory Map
- Physical Layer Registers
- Transport and Logical Layer Registers
- Capability Registers (CARs)
- Command and Status Registers (CSRs)
- Maintenance Interrupt Control Registers
- Transmit Maintenance Registers
- Transmit Port-Write Registers
- Receive Port-Write Registers
- Input/Output Master Address Mapping Registers
- Input/Output Master Interrupts
- Input/Output Slave Mapping Registers
- Input/Output Slave Interrupts
- Input/Output Slave Pending Transactions
- Error Management Registers
- Doorbell Message Registers
- 7. Testbench
- A. Initialization Sequence
- B. Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1
- Additional Information