Altera RapidIO II MegaCore Function User Manual
Page 21
Chapter 2: Getting Started
2–3
IFiles Generated for Altera IP Cores by Qsys (Legacy Parameter Editor)
August 2014
Altera Corporation
RapidIO II MegaCore Function
User Guide
I
Files Generated for Altera IP Cores by Qsys (Legacy Parameter Editor)
Generation of the IP core from Qsys produces the following output in Quartus II
software version 14.0 and previous.
In the case of the RapidIO II IP core you generate from the Qsys IP Catalog in the
Quartus II software v14.0:
■
The testbench script appears in <Qsys system>/simulation/<vendor>.
■
The testbench files appear in <Qsys system>/simulation/submodules/tb.
■
The IP core simulation files appear in
<Qsys system>/simulation/submodules/<vendor>
.
The RapidIO II IP core does not generate an example design.
Figure 2–2. IP Core Generated Files (Legacy Parameter Editor)
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
<Project Directory>
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
<your_ip>.qip - Lists files for synthesis
testbench - Simulation testbench files
1
<testbench_hdl_files>
<simulator_vendor> - Testbench for supported simulators
<simulation_testbench_files>
<your_ip>.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
<your_ip>.sip - NativeLink simulation integration file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
<your_ip> - IP core variation files
<your_ip>.qip or .qsys - System or IP integration file
<your_ip>_generation.rpt - IP generation report
<your_ip>.bsf - Block symbol schematic file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation startup scripts
1
<your_ip>.html - Contains memory map
<your_ip>.sopcinfo - Software tool-chain integration file
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist
1
<your_ip>.debuginfo - Lists files for synthesis
<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models
2
<your_ip>_tb - Testbench for supported simulators
<your_ip>_tb.v or .vhd - Top-level HDL testbench file