Altera RapidIO II MegaCore Function - Manual (Page 201)

Chapter 7: Testbench 7–7
Testbench Sequence
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
The NREAD request packets are received by the DUT and are translated into
Avalon-MM read transactions that are presented across the sister_rio module‘s I/O
master Avalon-MM interface. The sister_iom128_rd_wr_slave_bfm module checks the
read operations and returns data by calling the sister_iom128_rd_wr_slave_bfm
write_read_data
task. This task drives the data and read datavalid control signals
on the Avalon-MM master read port of the sister_rio module.
The returned data is expected at the DUT’s I/O Avalon-MM slave interface. The
ios_128_rd_wr_master_bfm read_data task captures the read data. The read data and
the expected value are then compared to ensure that they are equal.
NWRITE_R Transactions
To perform NWRITE_R operations, one register in the IP core must be reconfigured as
shown in
Table 7–3 .
With the setting in Table 7–3 , any write operation presented across the Input/Output
Avalon-MM slave module's Avalon-MM write interface is translated to a RapidIO
NWRITE_R
transaction. The Avalon-MM write address must map to the range specified
for the I/O Slave window 0.
To initialize testing of the new NWRITE_R completion indication feature, the test first
checks that the PENDING_NWRITE_RS field of the Input/Output Slave Pending
NWRITE_R Transactions
register has value 0, before setting the Input/Output Slave
Mapping Window 0 Control register and starting the sequence of NWRITE_R
transactions.
The testbench generates a predetermined series of burst writes across the
Input/Output Avalon-MM slave module's Avalon-MM write interface on the DUT.
These write bursts are each converted into NWRITE_R request packets sent over the
RapidIO Serial interface. The testbench cycles from 16 to 256 in steps of 8 bytes. Two
tasks are invoked to carry out the burst writes, rw_addr_data and rw_data. The
rw_addr_data
task initiates the burst and the rw_data task completes the burst.
At the sister_rio module, the NWRITE_R request packets are received and presented
across the I/O master Avalon-MM interface as write transactions. The testbench calls
the sister_iom128_rd_wr_slave_bfm read_write_data task to capture the written
data. The written data is checked against the expected value.
Table 7–3. NWRITE_R Transactions
Module
Register
Address
Name Value Description
rio 0x1040C
Input/Output Slave
Mapping Window 0
Control
32'h00CD_0001
or 32'hCDCD_0001
Sets the DESTINATION_ID for outgoing
transactions to the value 0x55 or 0x5555,
depending on the device ID width of the
sister_rio. This value matches the base
device ID of the sister_rio module. Enables
NWRITE_R
operations.