Altera RapidIO II MegaCore Function - Manual (Page 172)

6–34 Chapter 6: Software Interface
Transport and Logical Layer Registers
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Maintenance Interrupt Control Registers
Table 6–39 and Table 6–40 describe the registers that relate to the Maintenance module
interrupts. If any of these error conditions are detected and if the corresponding
Interrupt Enable bit is set, the mnt_mnt_s_irq signal is asserted.
Large_base_deviceID (1) [15:0]
RW
This is the base ID of the device in a large common transport
system. This field value is valid only for endpoint devices.
The value of this field appears on the
large_base_device_id
output signal.
16'hFFFF
RO Reserved if the system does not support 16-bit device ID.
Note to Table 6–36 :
(1) In a small common transport system, the Base_deviceID field is Read-Write and the Large_base_deviceID field is Read-only. In a large
common transport system, the Base_deviceID field is Read-only and the Large_base_deviceID field is Read-Write.
Table 6–36. Base Device ID CSR—Offset: 0x60 (Part 2 of 2)
Field Bits Access Function Default
Table 6–37. Host Base Device ID Lock CSR—Offset: 0x68
Field Bits Access Function Default
RSRV [31:16] RO Reserved 16'h0
HOST_BASE_DEVICE_ID [15:0] RW (1)
This is the base device ID for the processing element
that is initializing this processing element.
16'hFFFF
Note to Table 6–37 :
(1) Write once; can be reset. For more information, refer to §3.5.2 of the RapidIO Interconnect Specification v2.2 Part 3: Common Transport
Specification.
Table 6–38. Component Tag CSR—Offset: 0x6C
Field Bits Access Function Default
COMPONENT_TAG [31:0] RW This is a component tag for the processing element. 32'h0
Table 6–39. Maintenance Interrupt—Offset: 0x10080 (Part 1 of 2)
Field Bits Access Function Default
RSRV [31:7] RO Reserved 25'h0
PORT_WRITE_ERROR [6] RW1C Port-write error 1'b0
PACKET_DROPPED [5] RW1C
A received port-write packet was dropped. A port-write packet is
dropped under the following conditions:
■ A port-write request packet is received but port-write
reception has not been enabled by setting bit
PORT_WRITE_ENABLE
in the Rx Port Write Control
register.
■ A previously received port-write has not been read out from
the Rx Port Write register.
1'b0
PACKET_STORED [4] RW1C
Indicates that the IP core has received a port-write packet and
that the payload can be retrieved using the Register Access
Avalon-MM slave interface.
1'b0
RSRV [3] RO Reserved 1'b0