Altera RapidIO II MegaCore Function - Manual (Page 196)

7–2 Chapter 7: Testbench
Testbench Overview
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
■ NWRITE_R
■ NWRITE
■ NREAD
■ DOORBELL messages
■ MAINTENANCE writes and reads
■ MAINTENANCE port writes and reads
1 Your specific variation may not have all of the interfaces enabled. If an interface is not
enabled, the transactions supported by that interface are not exercised by the
testbench.
In addition, the RapidIO II IP core modules implement the following features:
■ Multicast-event control symbol transmission and reception. The RapidIO II IP core
under test generates and transmits multicast-event control symbols in response to
transitions on its send_multicast_event input signal. The sister module checks
that these control symbols arrive as expected.
■ Disabled destination ID checking, or not, selected at configuration.
■ Indication of NWRITE_R transactions that do not complete before the end of the
test sequence.
■
Figure 7–1. RapidIO II IP Core Testbench
PHY PHY
Avalon-MM
sister_rio
Serial
RapidIO
Interface
Avalon-MM
Avalon-ST
DUT
Avalon-ST
Maintenance
Slave
sister_mnt_master_bfm
Maintenance
Master
Maintenance
Slave
Maintenance
Master
mnt_master_bfm
sister_pt_hdr_bfm
sister_pt_pld_bfm
tx_pt_src_bfm
I/O
Master
I/O
Slave
ios_128_rd_wr_master_bfm
iom128_rd_wr_slave_bfm
sister_ios_128_rd_wr_master_bfm
sister_iom128_rd_wr_slave_bfm I/O
Master
I/O
Slave
sister_drbl_master_bfm
sister_sys_mnt_master_bfm
Register
Access
Slave
Doorbell
Slave
Register
Access
Slave
Doorbell
Slave
drbl_master_bfm
sys_mnt_master_bfm
Pass-
Through
Pass-
Through