Altera RapidIO II MegaCore Function - Manual (Page 216)

Info–4 Additional Information
Document Revision History
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
June 2014,
continued
Continued on
next page
14.0
■ Modified description of Port 0 Attributes Capture CSR (offset 0x348, Table 6–76
on page 6–51 ).
■ Added new allowed value 2’b100 (Implentation specific) for INFO_TYPE field of This
category includes errors that do not describe a packet or control symbol, and for
which information is updated in this register but not in the Port 0 Packet/Control
Symbol Capture 0-3
CSRs. Updated descriptions of other fields in the register to
account for the new allowed value.
■ Clarified that the value in the ERROR_TYPE field is based on the RapidIO big Endian
view of the bit number. Therefore, for correct correspondence with error bits in Port 0
Error Detect CSR, you must subtract the ERROR_TYPE value from 31.
■ Corrected Chapter 7, Testbench to state that the Altera-provided testbench does not
generate packets with ftype 9.
■ Corrected number of TX Maintenance windows indicated in Chapter 6, Software Interface .
The IP core has two TX Maintenance windows, not 16 as was previously indicated by the
address range and name for TX Maintenance Window registers in the Extended Features
and Implementation-Defined Registers Memory Map table (
Table 6–4 on page 6–4 ) and
in “Transmit Maintenance Registers” on page 6–35 .
■ Corrected descriptions of IDLE2 Received bit in LP-Serial Lane n Status 1 CSR
(
Table 6–18 on page 6–23 ) and CMD changed bit in LP-Serial Lane n Status 3 CSR
( Table 6–20 on page 6–24 ). Removed the corresponding fields from the description of
LP-Serial Lane n Status 2 CSR - Lane n Interrupt Enable ( Table 6–19 on
page 6–24 ). Neither of these two conditions triggers an interrupt.
■ Fixed assorted typos:
■ Corrected the width of the values of the destinationID and sourceID fields of the
gen_tx_data
bus in the Avalon-ST pass-through interface usage example User
Sending Read Request and Receiving Read Response to match field width.
■ Corrected width of default value for ExtendedFeaturesPtr field in Assembly
Information CAR
(offset 0x0C, Table 6–25 on page 6–27 ).
■ Corrected default value for LP-Serial Lane n Status 4 register bit [28]
(Scrambling/Descrambling enabled) (
Table 6–21 on page 6–25 ).
■ Corrected access mode for LP-Serial Lane n Status 4 register bit [30] (Impl
defined
) ( Table 6–21 on page 6–25 ).
■ Corrected bit range for Connected port transmit emphasis Tap (-1) status
field in LP-Serial Lane n Status 1 register (
Table 6–18 on page 6–23 ).
■ Corrected offset for Port 0 Link Maintenance Response register in the Extended
Features and Implementation-Defined Registers Memory Map table (
Table 6–4 on
page 6–4 ).
■ Corrected description of RESPONSE_VALID bit of Port 0 Link Maintenance
Response CSR (offset 0x140,
Table 6–10 on page 6–9 ). The link-request
control symbol is the trigger, not a fictitious link-response signal.
■ Corrected Maintenance Avalon-MM master signal names in Figure 4–17 on page 4–40
and Figure 4–19 on page 4–43 .
■ In Number of Link-Request Attempts Before Declaring Fatal Error parameter
comparison in
Appendix B, Differences Between RapidIO II MegaCore Function v12.1
and RapidIO MegaCore Function v12.1 , corrected the name of the relevant control
symbol. Changed erroneous mention of link-request reset-device control
symbol to link-request input-status control symbol.
■ Assorted minor typos.
Date Version Changes