Altera RapidIO II MegaCore Function - Manual (Page 60)

4–18 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
The RapidIO II IP core receives both transaction requests on the RapidIO link and
sends them to the Logical layer Avalon-MM master module. If the RapidIO link
partner is also an Altera RapidIO II IP core, the timing diagrams in
“Input/Output
Avalon-MM Slave Module Timing Diagrams” on page 4–31 show the same
transactions as they originate on the Avalon-MM interface of the RapidIO link
partner’s Input/Output Avalon-MM slave module.
Figure 4–6. NREAD Transaction on the Input/Output Avalon-MM Master Interface
sysclk
iom_rd_wr_waitrequest
iom_rd_wr_read
iom_rd_wr_address[31:0]
iom_rd_wr_readdatavalid
iom_rd_wr_readresponse
iom_rd_wr_readdata[127:0]
iom_rd_wr_burstcount[4:0]
iom_rd_wr_byteenable[15:0]
00000000 Adr0 Adr1
r0 r1 r2
00 01 02
00 00F0 FFFF
Figure 4–7. NWRITE Transaction on the Input/Output Avalon-MM Master Interface
sys_clk
iom_rd_wr_waitrequest
iom_rd_wr_write
iom_rd_wr_address[31:0]
iom_rd_wr_writedata[127:0]
iom_rd_wr_byteenable[15:0]
iom_rd_wr_burstcount[7:0]
AdrA AdrB
w1 w2 w3 w4 w5 w0
FFFF
02 04