Altera RapidIO II MegaCore Function - Manual (Page 175)

Chapter 6: Software Interface 6–37
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Receive Port-Write Registers
Table 6–48 through Table 6–50 describe the receive port-write registers.
Refer to “Port-Write Reception Module” on page 4–80 for information about receiving
port write MAINTENANCE packets.
Input/Output Master Address Mapping Registers
Table 6–51 through Table 6–53 describe the Input/Output master registers. When the
IP core receives an NREAD, NWRITE, NWRITE_R, or SWRITE request packet, the RapidIO
address has to be translated into a local Avalon-MM address. If you specify at least
one address mapping window, the translation involves the base, mask, and offset
registers. The IP core has up to 16 register sets, one for each address mapping
window. The 16 possible register address offsets are shown in the table titles.
Table 6–46. Tx Port Write Status—Offset: 0x10204
Field Bits Access Function Default
RSRV [31:0] RO Reserved 31'h0
Table 6–47. Tx Port Write Buffer n—Offset: 0x10210 – 0x1024C
Field Bits Access Function Default
PORT_WRITE_DATA_n [31:0] RW
Port-write data. This buffer is implemented in memory and is
not initialized at reset.
32'hx
Table 6–48. Rx Port Write Control—Offset: 0x10250
Field Bits Access Function Default
RSRV [31:2] RO Reserved 30'h0
CLEAR_BUFFER [1] RW Clear port-write buffer. Write 1 to activate. Always read 0. 1'b0
PORT_WRITE_ENA [0] RW
Port-write enable. If set to 1, port-write packets are accepted.
If set to 0, port-write packets are dropped.
1'b1
Table 6–49. Rx Port Write Status—Offset: 0x10254
Field Bits Access Function Default
RSRV [31:6] RO Reserved 26'h0
PAYLOAD_SIZE [5:2] RO
Packet payload size in number of double words. If the size is
zero, the payload size is single word.
4'h0
RSRV [1] RO Reserved 1'b0
PORT_WRITE_BUSY [0] RO
Port-write busy. Set if a packet is currently being stored in the
buffer or if the packet is stored and has not been read.
1'b0
Table 6–50. Rx Port Write Buffer n—Offset: 0x10260 – 0x1029C
Field Bits Access Function Default
PORT_WRITE_DATA_n [31:0] RO
Port-write data. This buffer is implemented in memory and is
not initialized at reset.
32'hx