Altera RapidIO II MegaCore Function - Manual (Page 173)

Chapter 6: Software Interface 6–35
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Transmit Maintenance Registers
Table 6–41 through Table 6–44 describe the transmitter maintenance registers. When
transmitting a MAINTENANCE packet, an address translation process occurs, using a
base, mask, offset, and control register. Two groups of four registers can exist. The two
register address offsets are shown in the table titles. For more details on how to use
these windows, refer to
“Initiating MAINTENANCE Read and Write Transactions”
on page 4–34 .
RSRV [2] RO Reserved 1'b0
WRITE_OUT_OF_BOUNDS [1] RW1C
If the address of an Avalon-MM write transfer presented at the
Maintenance Avalon-MM slave interface does not fall within any
of the enabled Tx Maintenance Address translation windows,
then it is considered out of bounds and this bit is set.
1'b0
READ_OUT_OF_BOUNDS [0] RW1C
If the address of an Avalon-MM read transfer presented at the
Maintenance Avalon-MM slave interface does not fall within any
of the enabled Tx Maintenance Address translation windows,
then it is considered out of bounds and this bit is set.
1'b0
Table 6–39. Maintenance Interrupt—Offset: 0x10080 (Part 2 of 2)
Field Bits Access Function Default
Table 6–40. Maintenance Interrupt Enable—Offset: 0x10084
Field Bit Access Function Default
RSRV [31:7] RO Reserved 25'h0
PORT_WRITE_ERROR [6] RW Port-write error interrupt enable 1'b0
RX_PACKET_DROPPED [5] RW Rx port-write packet dropped interrupt enable 1'b0
RX_PACKET_STORED [4] RW Rx port-write packet stored in buffer interrupt enable 1'b0
RSRV [3:2] RO Reserved 2'b00
WRITE_OUT_OF_BOUNDS [1] RW Tx write request address out of bounds interrupt enable 1'b0
READ_OUT_OF_BOUNDS [0] RW Tx read request address out of bounds interrupt enable 1'b0
Table 6–41. Tx Maintenance Mapping Window n Base—Offset: 0x10100, 0x10110
Field Bits Access Function Default
BASE [31:3] RW
Start of the Avalon-MM address window to be mapped. The
three least significant bits of the 32-bit base are assumed to be
zero.
29'h0
RSRV [2:0] RO Reserved 3'h0
Table 6–42. Tx Maintenance Mapping Window n Mask—Offset: 0x10104, 0x10114
Field Bits Access Function Default
MASK [31:3] RW
Mask for the address mapping window. The three least
significant bits of the 32-bit mask are assumed to be zero.
29'h0
WEN [2] RW
Window enable. Set to one to enable the corresponding
window.
1'b0
RSRV [1:0] RO Reserved 2'h0