Altera RapidIO II MegaCore Function - Manual (Page 124)

4–82 Chapter 4: Functional Description
Error Detection and Management
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
■ Unsupported Transaction is declared when a request packet carries a transaction
type that is not supported in the Destination Operations CAR ( Table 6–29 on
page 6–30 ), whether an ATOMIC transaction type, a reserved transaction type, or an
implementation defined transaction type.
■ Illegal Transaction Decode is declared when a request packet for a supported
transaction is too short or if it contains illegal values in some of its fields such as in
these examples:
■ Request packet with priority = 3.
■ NWRITE , NWRITE_R, or SWRITE request packets without payload.
■ NWRITE or NWRITE_R request packets with reserved wrsize and wdptr
combination.
■ NWRITE , NWRITE_R, SWRITE, or NREAD request packets for which the address does
not match any enabled address mapping window.
■ NREAD request packet with payload.
■ NREAD request with rdsize that is not an integral number of transfers on all byte
lanes. (The Avalon-MM interface specification requires that all byte lanes be
enabled for read transfers. Therefore, Read Avalon-MM master modules do not
have a byteenable signal).
■ Payload size does not match the size indicated by the rdsize or wrsize and
wdptr
fields.
Response Packets with ERROR Status
An ERROR response packet is sent for NREAD and NWRITE_R and Type 5 ATOMIC request
packets that cause an Illegal Transaction Decode error to be declared. An ERROR
response packet is also sent for NREAD requests if the iom_rd_wr_readresponse input
signal is asserted through the final cycle of the Avalon-MM read transfer.
Avalon-ST Pass-Through Interface
Packets with valid CRCs that are not recognized as being targeted to one of the
implemented Logical layer modules are passed to the Avalon-ST pass-through
interface for processing by user logic.
The RapidIO II IP core also provides hooks for user logic to report any error detected
by a user-implemented Logical layer module attached to the Avalon-ST pass-through
interface.