Altera RapidIO II MegaCore Function - Manual (Page 64)

4–22 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
The RapidIO II IP core assigns a time-out value to each outbound request that
requires a response—each NWRITE_R or NREAD transaction. The time-out value is the
sum of the VALUE field of the Port Response Time-Out Control register (
Table 6–8 on
page 6–8 ) and the current value of a free-running counter. When the counter reaches
the time-out value, if the transaction has not yet received a response, the transaction
times out. Refer to
Table 6–8 for information about the duration of the time-out.
Tracking I/O Write Transactions
The following three registers are available to software to track the status of I/O write
transactions:
■ The Input/Output Slave Avalon-MM Write Transactions register described in
Table 6–63 on page 6–42 holds a count of the write transactions that have been
initiated on the write Avalon-MM slave interface.
■ The Input/Output Slave RapidIO Write Requests register described in
Table 6–64 on page 6–42 holds a count of the RapidIO write request packets that
have been transferred to the Transport layer.
■ The Input/Output Slave Pending NWRITE_R Transactions register described in
Table 6–62 on page 6–41 holds a count of the NWRITE_R requests that have been
issued but have not yet completed.
You can use these registers to determine if a specific I/O write transaction has been
issued or if a response has been received for any or all issued NWRITE_R requests.
Defining the Input/Output Avalon-MM Slave Address Mapping Windows
When you specify the value for Number of Tx address translation windows in the
RapidIO II parameter editor, you determine the number of address translation
windows available for translating incoming Avalon-MM read and write transactions
to RapidIO read and write requests.
You must program the Input/Output Slave Mapping Window registers to support the
address ranges you wish to distinguish. You can disable an address translation
window that is available in your configuration, but the maximum number of
windows you can program is the number you specify in the RapidIO II parameter
editor with the Number of Tx address translation windows value.
The RapidIO II IP core includes one set of Input/Output Slave Mapping Window
registers for each translation window. The following registers define address
translation window n:
■ A base register: Input/Output Slave Mapping Window n Base ( Table 6–56 on
page 6–39 )
■ A mask register: Input/Output Slave Mapping Window n Mask ( Table 6–57 )
■ An offset register: Input/Output Slave Mapping Window n Offset ( Table 6–58 )
■ A control register: Input/Output Slave Mapping Window n Control ( Table 6–59 )
The control register stores information the RapidIO II IP core uses to prepare the
RapidIO packet header, including the target device’s destination ID, the request
packet's priority, and to select between the three available write request packet types:
NWRITE
, NWRITE_R and SWRITE. Figure 4–9 on page 4–24 illustrates the address
mapping.