Altera RapidIO II MegaCore Function - Manual (Page 139)

August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
6. Software Interface
The RapidIO IP core supports the following sets of registers that control the RapidIO
IP core or query its status:
■ Standard RapidIO capability registers—CARs
■ Standard RapidIO command and status registers—CSRs
■ Extended features registers
■ Implementation defined registers
■ Doorbell specific registers
Some of these register sets are supported by specific RapidIO II IP core layers only.
This chapter organizes the registers by the layers they support. The Physical layer
registers are described first, followed by the Transport and Logical layers registers.
All of the registers are 32 bits wide and are shown as hexadecimal values. The
registers can be accessed only on a 32-bit (4-byte) basis. The addressing for the
registers therefore increments by units of 4.
1
Reserved fields are labeled in the register tables. These fields are reserved for future
use and your design should not write to nor rely on a specific value being found in
any reserved field or bit.
The following sets of registers are accessible through the Maintenance Avalon-MM
slave interface.
■ CARs—Capability registers
■ CSRs—Command and status registers
■ Extended features registers
■ Implementation defined registers
A remote device can access these registers only by issuing read/write MAINTENANCE
operations destined for the local device. The RapidIO II IP core routes read/write
MAINTENANCE
requests that address the IP core registers internally.
The doorbell registers can be accessed through the Doorbell Avalon-MM slave
interface. These registers are implemented only if you turn on Enable Doorbell
support
in the RapidIO II parameter editor.
Table 6–1 lists the access codes used tin the individual register descriptions to specify
the type of register bits.
Table 6–1. Register Access Codes (Part 1 of 2)
Code Description
RW Read/write
RO Read-only
RC Read to clear