Altera RapidIO II MegaCore Function - Manual (Page 25)

Chapter 2: Getting Started 2–7
Integrating Your IP Core in Your Design
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Altera recommends that you implement the reconfiguration controller with an Altera
Transceiver Reconfiguration Controller. The Transceiver Reconfiguration Controller
performs offset cancellation during bring-up of the transceiver channels.
The Transceiver Reconfiguration Controller is available in the IP catalog. You must
add it to your design and connect it to the RapidIO II IP core reconfiguration signals.
In the Transceiver Reconfiguration Controller parameter editor, you select the features
of the transceiver that can be dynamically reconfigured. However, you must ensure
that the following two features are turned on:
■ Enable PLL calibration
■ Enable Analog controls
An informational message in the RapidIO II parameter editor tells you the number of
reconfiguration interfaces you must configure in your dynamic reconfiguration block.
You must configure the Transceiver Reconfiguration Controller Number of
reconfiguration interfaces
parameter with this value. For more information, refer to
Table 5–7 on page 5–5 .
The Reconfiguration Controller communicates with the RapidIO II IP core on two
busses:
■ reconfig_to_xcvr (output)
■ reconfig_from_xcvr (input)
Each of these busses connects to the bus of the same name in the RapidIO II IP core.
You must also connect the following Reconfiguration Controller signals:
■ mgmt_clk_clk
■ mgmt_rst_reset
■ reconfig_busy
f
For information about the Altera Transceiver Reconfiguration Controller, refer to the
Altera Transceiver PHY IP Core User Guide .
Transceiver PHY Reset Controller
You must add an Altera Transceiver PHY Reset Controller IP core to your design, and
connect it to the RapidIO II IP core reset signals. This block implements a reset
sequence that resets the device transceivers correctly. The default parameter settings
of the Altera Transceiver PHY Reset Controller IP core are compatible with the
RapidIO II IP core requirements. For more information, refer to
“Reset for RapidIO II
IP Cores” on page 4–4 .
f For information about the Altera Transceiver PHY Reset Controller IP core, refer to
the
Altera Transceiver PHY IP Core User Guide or the Arria 10 Transceiver PHY User
Guide .