Altera RapidIO II MegaCore Function - Manual (Page 214)

Info–2 Additional Information
Document Revision History
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
June 2014
Continued on
next page 14.0
■ Modified Chapter 2, Getting Started to describe the new Quartus II software v14.0 IP
Catalog
■ Modified Chapter 3, Parameter Settings to document the new location of the Extended
features pointer parameter in the RapidIO II parameter editor. The Extended features
pointer parameter is now on the Command and Status Registers tab instead of the
Capability Registers tab. This change dates from the Quartus II software v13.1.
■ Changed bit range of ext_mnt_address from [23:2] to [21:0] and explained the address
is a word address, in
Table 4–4 on page 4–8 .
■ Explained that drbell_s_address is a word address and ios_rd_wr_address is a
quad-word address, in
Table 4–22 on page 4–46 and Table 4–9 on page 4–20 ,
respectively.
■ Changed bit range of mnt_s_address from [25:2] to [23:0].
■ In Table 4–13 on page 4–33 , modified the bit range and explained the address is a
word address.
■ Added correct bit ranges to the config_offset calculation in “Defining the
Maintenance Address Translation Windows” on page 4–34 .
■ Modified the definition of the wdptr field in Maintenance Read and Maintenance Write
request packets the IP core transmits on the RapidIO link for consistency with the new
bit range numbering, in example RapidIO packets listed in
Table 4–17 and Table 4–20 .
■ Clarified that generating this IP core does not generate an Altera-provided VHDL
testbench, only a Verilog HDL testbench. Added this information in
Chapter 2, Getting
Started and in Chapter 7, Testbench .
■ Clarified in description of ERR_RATE_COUNTER field of the Port 0 Error Rate CSR
(offset 0x386,
Table 6–81 on page 6–52 ) that this field increments only by one if multiple
errors are flagged in the same clock cycle.
■ Clarified in Table 4–24 on page 4–49 that Avalon-ST pass-through interface
gen_tx_valid signal must be continuously asserted from the assertion of
gen_tx_startofpacket until the deassertion of gen_tx_endofpacket.
■ Added Table 4–25 on page 4–50 and Table 4–26 on page 4–51 , which list header
information format in gen_tx_data for all supported transaction types and both device ID
widths.
■ Added four new Avalon-ST pass-through interface usage examples, including examples
with device ID width 8.
Date Version Changes