Achronix ACE Version 5.0 User Manual
Page 45
Editors
Chapter 3. Concepts
Memory Timing Page
The Memory Timing Page allows the user to configure the memory timings for the DDR3 Interface.
DDR3 Editor Memory Timing Page Options
Option
Description
AL/CL/CWL
Additive latency value
Additive Latency (AL) in clock cycles
CAS Latency
CAS Latency (CL) in clock cycles
CAS Write Latency
CAS Write Latency (CWL) in clock cycles
Auto-Refresh
Controller Refresh Enable
When enabled, the DDR Controller will handle DDR Memory Refreshes
Refresh Period
Number of clocks between Refresh commands
Command-to-Command Delays
Activate To Activate (Diff
Bank)
Minimum number of clock cycles from Activate to Activate in different
Banks
Activate To Activate (Same
Bank)
Minimum number of clock cycles from Activate to Activate/Auto Refresh
in the same Bank
Activate To Precharge
Minimum number of clock cycles from Activate to Precharge
Activate To R/W
Minimum number of clock cycles between Activate and Read/Write
Auto-refresh To Activate
(Same Bank)
Minimum number of clock cycles from Auto Refresh to Activate/Auto
Refresh in the same Bank
Bank Activate Period
Four Bank activate period
Loadmode To Activate
Minimum clock cycles from Loadmode to Activate command
Loadmode To Any
Minimum clock cycles from Loadmode to Any command
Precharge To Activate
Minimum clock cycles from Precharge to Activate
Read To Precharge
Minimum clock cycles from Read to Precharge
Read To Read (Diff Bank)
Minimum clock cycles from Read to Read (Different Banks)
Read To Write
Read to Write delay in clock cycles
Reset High to Clock High
Minimum clock cycles from memory reset high to cke high
Self-refresh to Non-DLL
command
Minimum clock cycles from Self-refresh to Non-DLL command
Self-refresh to Non-Read
command
Minimum clock cycles from Self-refresh to Non-Read command
Write To Precharge
Minimum clock cycles from write to Precharge
Write To Read
Minimum clock cycles from Write to Read
Write To Read (Diff Bank)
Minimum clock cycles from Write to Read (Different Banks)
Write To Write (Diff Bank)
Minimum clock cycles from Write to Write (Different Banks)
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UG001 Rev. 5.0 - 5th December 2012