Achronix ACE Version 5.0 User Manual
Page 38
Editors
Chapter 3. Concepts
Output Register
Clock Enable Priority
Y
The Clock Enable Priority defines the priority
of the outregceb clock enable input relative
to the rstregb reset input during an assertion
of the rstregb signal on the output register of
Port B. The value rstreg allows the Port B
output register to be set/reset at the next
active edge of the Port B clock without
requiring a specific value on the outregceb
output register clock enable input. The value
regce
requires that the outregceb output
register clock enable input is high for the
output register set/reset operation to occur at
the next active edge of the Port B clock.
Output Register Reset
Active-High
Y
When this is enabled, the output register has
an active-high synchronous reset. Otherwise,
the output register reset will be active-low.
Total Memory Size
Port A Address Depth x Port A Data Width
Number of BRAMs Used
The total number of BRAM instances which
will be used to create a BRAM wrapper of the
configured width(s) and depth(s).
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