Texas Instruments TMS320C2XX User Manual
Page 584
Index
Index-21
status registers ST0 and ST1
addresses and reset values
bits
clear control bit (CLRC instruction)
introduction
load (LST instruction)
load data page pointer (LDP instruction)
modify auxiliary register pointer (MAR instruc-
tion)
quick reference
set control bit (SETC instruction)
set product shift mode (SPM instruction)
store (SST instruction)
STB bit
STRB (external access active strobe)
SUB instruction
SUBB instruction
SUBC instruction
SUBS instruction
SUBT instruction
subtract.
See accumulator instructions
SXM (sign-extension mode bit)
definition
effect on CALU (central arithmetic logic
unit)
effect on input shifter
synchronous serial port
See also synchronous serial port registers
basic operation
bit input from CLKR pin (IN0 bit)
block diagram
burst mode (introduction)
CLKR pin as bit input (IN0 bit)
clock source for transmission (MCM bit)
components
configuration
continuous mode (introduction)
controlling and resetting
digital loopback mode
emulation modes
error conditions
burst mode
continuous mode
features
synchronous serial port
(continued)
FIFO buffers
detecting data in receive FIFO buffer (RFNE
bit)
detecting empty transmit FIFO buffer (TCOMP
bit)
introduction
managing contents with SDTR
frame sync modes (FSM bit)
frame sync source for transmission (TXM
bit)
interrupts (XINT and RINT)
flag bits
mask bits
priorities
receive (RINT)
controlling (FR1 and FR0 bits)
transmit (XINT)
controlling (FT1 and FT0 bits)
using
vector locations
introduction
overflow in receiver
burst mode
continuous mode
detecting (OVF bit)
overview
pins
receiver operation
burst mode
continuous mode
registers (overview)
reset conditions
resetting
receiver (RRST bit)
transmitter (XRST bit)
selecting mode of operation
selecting transmit clock source
selecting transmit frame sync source
signals
testing
transmitter operation
burst mode with external frame sync
burst mode with internal frame sync
continuous mode with external frame
sync
continuous mode with internal frame
sync