Texas Instruments TMS320C2XX - Manual (Page 541)

F-4
CALU: See central arithmetic logic unit (CALU).
carry bit: Bit 9 of status register ST1; used by the CALU for extended
arithmetic operations and accumulator shifts and rotates. The carry bit
can be tested by conditional instructions.
central arithmetic logic unit (CALU): The 32-bit wide main arithmetic logic
unit for the ’C2xx CPU that performs arithmetic and logic operations. It
accepts 32-bit values for operations, and its 32-bit output is held in the
accumulator.
CIO0–CIO3 bits: Bits 0–3 of the asynchronous serial port control register
(ASPCR); they individually configure pins IO0–IO3 as either inputs or
outputs. For example, CIO0 configures the IO0 pin. See also
DIO0–DIO3
bits; IO0–IO3 bits.
CLK register: CLKOUT1-pin control register. Bit 0 of determines whether
the CLKOUT1 signal is available at the CLKOUT1 pin.
CLKIN: Input clock signal. A clock source signal supplied to the on-chip
clock generator at the CLKIN/X2 pin or generated internally by the on-
chip oscillator. The clock generator divides or multiplies CLKIN to pro-
duce the CPU clock signal, CLKOUT1.
CLKMOD pin: (On the ’C209 only) Determines whether the on-chip clock
generator is running in the divide-by-two or multiply-by-two mode. See
also
clock mode.
CLKOUT1: Master clock output signal. The output signal of the on-chip
clock generator. The CLKOUT1 high pulse signifies the CPU’s logic
phase (when internal values are changed), and the CLKOUT1 low pulse
signifies the CPU’s latch phase (when the values are held constant).
CLKOUT1 cycle: See CPU cycle.
CLKOUT1-pin control register: See CLK register.
CLKR: Receive clock input pin. A pin that receives an external clock signal
to clock data from the DR pin into the synchronous serial port receive shift
register (RSR).
CLKX: Transmit clock input/output pin. A pin used to clock data from the syn-
chronous serial port transmit shift register to the DX pin. If the serial port
is configured to accept an external clock, this pin receives the clock sig-
nal. If the port is configured to generate an internal clock, this pin trans-
mits the clock signal.
Glossary