Texas Instruments TMS320C2XX User Manual
Page 570

Index
Index-7
data memory select pin (DS)
definition
shown in figure
data page 0
caution about test/emulation addresses
data page pointer (DP)
caution about initializing DP
definition
load (LDP instruction)
role in direct addressing
data read bus (DRDB)
data write bus (DWEB)
data-read address bus (DRAB)
data-scaling shifter
at input of CALU
at output of CALU
data-write address bus (DWAB)
delta interrupts
description
enabling/disabling (DIM bit)
device reset
diagnostic applications
digital loopback mode
DIM bit
dimensions
12-pin header
14-pin header
mechanical, 14-pin header
DIO0–DIO3 (bits), detecting change on pins
IO0–IO3
direct addressing
description
examples
figure
opcode format
role of data page pointer (DP)
direct memory access (using HOLD opera-
tion)
during reset
example
terminating correctly
DIV1 and DIV2 pins
divide (SUBC instruction)
DLB bit
DMOV instruction
DP (data page pointer)
caution about initializing DP
definition
load (LDP instruction)
role in direct addressing
DR bit
DR pin
DRAB (data-read address bus)
DRDB (data read bus)
DS (data memory select pin)
definition
shown in figure
DSWS bit(s)
’C203/C204
’C209
dual-access RAM (DARAM)
configuration
’C203
’C204
’C209
11-8
description
DuPont connector
DWAB (data-write address bus)
DWEB (data write bus)
DX pin
E
EMU0/1
configuration
emulation pins
IN signals
rising edge modification
EMU0/1 signals
E-2, E-3, E-6, E-7, E-13, E-18
emulation
configuring multiple processors
JTAG cable
pins
timing calculations
using scan path linkers
emulation capability
emulation modes (FREE and SOFT bits)
asynchronous serial port
synchronous serial port
timer
emulation timing