Texas Instruments TMS320C2XX User Manual

Page 550

F-13

Glossary

IO0–IO3 bits:

Bits 0–3 of the IOSR. When pins IO0–IO3 are configured as

inputs, these bits reflect the current logic levels on the pins. For example,
the IO0 bit reflects the level on the IO0 pin. See also

CIO0–CIO3 bits;

DIO0–DIO3 bits.

IO0–IO3 pins:

Four pins that can be individually configured as inputs or out-

puts. These pins can be used for interfacing the asynchronous serial port
or as general-purpose I/O pins. See also

CIO0–CIO3 bits; DIO0–DIO3

bits; IO0–IO3 bits.

I/O-mapped register:

One of the on-chip registers mapped to addresses in

I/O (input/output) space. These registers, which include the registers for
the on-chip peripherals, must be accessed with the IN and OUT instruc-
tions. See also

memory-mapped register.

I/O status register (IOSR):

A register in the asynchronous serial port that

provides status information about signals IO0–IO3 and about transfers
in progress.

IOSR:

See

I/O status register (IOSR).

IR:

See

instruction register (IR).

IS:

I/O space select pin. The ’C2xx asserts IS to indicate an access to exter-

nal I/O space.

ISR:

See

interrupt service routine (ISR).

ISWS:

I/O-space wait-state bit(s). A value in the wait-state generator control

register (WSGR) that determines the number of wait states applied to
reads from and writes to off-chip I/O space. On the ’C209, ISWS is bit 2
of the WSGR; on other ’C2xx devices, ISWS is bits 11–9.

latch phase:

The phase of a CPU cycle during which internal values are held

constant. See also

logic phase; CLKOUT1.

local data space:

The portion of data-memory addresses that are not allo-

cated as global by the global memory allocation register (GREG). If none
of the data-memory addresses are allocated for global use, all of data
space is local. See also

global data space.

logic phase:

The phase of a CPU cycle during which internal values are

changed. See also

latch phase; CLKOUT1.

long-immediate value:

A 16-bit constant given as an operand of an

instruction that is using immediate addressing.

Glossary