Setc – Texas Instruments TMS320C2XX User Manual
Page 308
Set Control Bit
SETC
7-155
Assembly Language Instructions
Syntax
SETC
control bit
Operands
control bit:
Select one of the following control bits:
C
Carry bit of status register ST1
CNF
RAM configuration control bit of status register ST1
INTM
Interrupt mode bit of status register ST0
OVM
Overflow mode bit of status register ST0
SXM
Sign-extension mode bit of status register ST1
TC
Test/control flag bit of status register ST1
XF
XF pin status bit of status register ST1
SETC C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
0
1
0
0
1
1
1
1
1
0
1
SETC CNF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
1
0
0
0
1
0
0
1
1
1
1
1
0
1
SETC INTM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
SETC OVM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
0
0
0
0
1
0
0
1
1
1
1
1
0
1
SETC SXM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
0
0
0
1
0
0
1
1
1
1
1
0
1
SETC TC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
1
SETC XF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
1
1
0
0
1
0
0
1
1
1
1
1
0
1
Execution
Increment PC, then ...
1
→
control bit
Status Bits
None
Description
The specified control bit is set to 1. Note that LST may also be used to load
ST0 and ST1. See Section 3.5,
Status and Control Registers, on page 3-15
for more information on each control bit.
Opcode