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Texas Instruments TMS320C2XX User Manual

Page 244

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Load TREG

LT

7-91

Assembly Language Instructions

Syntax

LT

dma

Direct addressing

LT

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

n:

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–

LT

dma

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

1

1

0

0

1

1

0

dma

LT

ind [, ARn]

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

1

1

0

0

1

1

1

ARU

N

NAR

Note:

ARU, N, and NAR are defined in Section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...
(data-memory address)

TREG

Status Bits

None

Description

TREG is loaded with the contents of the specified data-memory address. The
LT instruction may be used to load TREG in preparation for multiplication. See
also the LTA, LTD, LTP, LTS, MPY, MPYA, MPYS, and MPYU instructions.

Words

1

Cycles for a Single LT Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1

1

1

1+p

SARAM

1

1

1, 2

1+p

External

1+d

1+d

1+d

2+d+p

† If the operand and the code are in the same SARAM block

Opcode

Cycles