Texas Instruments TMS320C2XX User Manual
Page 23
Tables
xxiv
9–1
SSP Interface Pins
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9–2
Run and Emulation Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–3
Controlling Transmit Interrupt Generation by Writing to Bits FT1 and FT0
. . . . . . . . . . . . .
9–4
Controlling Receive Interrupt Generation by Writing to Bits FR1 and FR0
9–5
Selecting Transmit Clock and Frame Sync Sources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–6
Run and Emulation Modes
10–1
Asynchronous Serial Port Interface Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–2
Common Baud Rates and the Corresponding BRD Values
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10–3
Configuring Pins IO0–IO3 with ASPCR Bits CIO0–CIO3
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10–4
Viewing the Status of Pins IO0–IO3 With IOSR Bits IO0–IO3 and DIO0–DIO3
11–1
’C209 Program-Memory Configuration Options
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11–2
’C209 Data-Memory Configuration Options
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11–3
’C209 On-Chip Registers Mapped to I/O Space
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11–4
’C209 Interrupt Locations and Priorities
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11–5
’C209 Input Clock Modes
A–1
Reset Values of the Status Registers
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A–2
Addresses and Reset Values of On-Chip Registers Mapped to Data Space
A–3
Addresses and Reset Values of On-Chip Registers Mapped to I/O Space
B–1
Symbols and Acronyms Used in the Instruction Set Summary
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B–2
Summary of Enhanced Instructions
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C–1
Shared Programs in This Appendix
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C–2
Task-Specific Programs in This Appendix
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E–1
14-Pin Header Signal Descriptions
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E–2
Emulator Cable Pod Timing Parameters
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