Texas Instruments TMS320C2XX - Manual (Page 575)

Index
Index-12
interrupt (continued)
phases of operation 5-15
priorities
’C203/C204 5-16
’C209 11-10
in interrupt acknowledgement process 5-19
registers
interrupt control register (ICR) 5-24
interrupt flag register (IFR) 5-20 to 5-22
’C209 11-12
interrupt mask register (IMR) 5-22 to 5-24
’C209 11-13
software interrupt
definition 5-15
instructions 5-27
special cases
clearing ICR flag bits 5-25
clearing IFR flag bit after INTR instruc-
tion 5-21
clearing IFR flag bits set by serial port inter-
rupts 5-21
controlling INT2 and INT3 with ICR 5-24
requesting INT2 and INT3 5-18
table 5-16
vector locations
’C203/C204 5-16
’C209 11-10
interrupt acknowledge signal (IACK) 11-13
interrupt control register (ICR) 5-24 to 5-38
bits 5-26
quick reference A-8
interrupt flag register (IFR) 5-20 to 5-38
bits
’C203/C204 5-21
’C209 11-12
clearing interrupts 5-20
quick reference A-6
interrupt latency
definition F-12
description 5-30
interrupt mask register (IMR) 5-22 to 5-38
bits
’C203/C204 5-23
’C209 11-13
in interrupt acknowledgement process 5-19
quick reference A-7
interrupt mode bit (INTM) 3-16
interrupt phases of operation 5-15
interrupt service routines (ISRs) 5-29
definition F-12
ISRs within ISRs 5-30
saving and restoring context 5-29
INTM (interrupt mode bit) 3-16
effect on power-down mode 5-36
in interrupt acknowledgement process 5-19
INTR instruction 7-71
introduction 5-27
operand (K) values
’C203/C204 5-16
’C209 11-10
introduction
TMS320 devices 1-2
TMS320C2xx devices 1-5
IO0–IO3 (bits) 10-13
reading current logic level on pins
IO0–IO3 10-16
IO0–IO3 (pins) 10-15 to 10-17
IOSR (I/O status register)
detecting change on pins IO0–IO3 10-16
quick reference A-14
reading current logic level on pins
IO0–IO3 10-16
IR (instruction register), definition F-11
IS (I/O space select pin)
definition 4-3
shown in figure 4-26
ISR (interrupt service routine) 5-29 to 5-30
definition F-12
ISRs within ISRs 5-30
saving and restoring context 5-29 to 5-30
ISWS bit(s)
’C203/C204 8-15
’C209 11-17
J
JTAG E-16
JTAG emulator
buffered signals E-10
connection to target system E-1 to E-25
no signal buffering E-10
K
key features of the ’C2x 1-6