Texas Instruments TMS320C2XX - Manual (Page 316)

Store Low PREG SPL
7-163 Assembly Language Instructions
Syntax SPL dma Direct addressing
SPL ind [, ARn] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
SPL dma
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 1 1 0 0 0 dma
SPL ind [, ARn]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 1 1 0 0 1 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3, Indirect Addressing Mode (page 6-9).
Execution Increment PC, then ...
16 LSBs of shifted (PREG)
→
data-memory address
Status Bits Affected by
PM
Description The 16 low-order bits of the PREG, shifted as specified by the PM bits, are
stored in data memory. First, the 32-bit PREG value is copied into the product
shifter, where it is shifted as specified by the PM bits. If the right-shift-by-6
mode is selected, the high-order bits are sign extended and the low-order bits
are lost. If a left shift is selected, the high-order bits are lost and the low-order
bits are zero filled. If PM = 00, no shift occurs. Then the 16 LSBs of the shifted
value are stored in data memory. Neither the PREG value nor the accumulator
value is modified by this instruction.
Words 1
Cycles for a Single SPL Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2 † 1+p
External 2+d 2+d 2+d 4+d+p
† If the operand and the code are in the same SARAM block
Opcode
Cycles