Texas Instruments TMS320C2XX User Manual

Page 118

Interrupts

5-19

Program Control

After an interrupt request is received by the CPU, the CPU must decide wheth-
er to acknowledge the request. Maskable hardware interrupts are acknowl-
edged only after certain conditions are met:

Priority is highest. When more than one hardware interrupt is requested
at the same time, the ’C2xx services them according to a set priority rank-
ing in which 1 indicates the highest priority. For the priorities of the hard-
ware interrupts, see subsection 5.6.2 (on page 5-16).

IMR mask bit is 1. The interrupt must be unmasked (enabled) in the inter-
rupt mask register (IMR), a 16-bit, memory-mapped register located at ad-
dress 0004h in data-memory space. The IMR contains mask bits for all the
maskable interrupts. INT2 and INT3 share one of the bits in the IMR. The
IMR is explained in subsection 5.6.5 on page 5-22.

INTM bit is 0. The interrupt mode (INTM) bit, bit 9 of status register ST0,
enables or disables all maskable interrupts:

When INTM = 0, all unmasked interrupts are enabled.

When INTM = 1, all unmasked interrupts are disabled.

INTM is set to 1 automatically when the CPU acknowledges an interrupt
(except when initiated by the TRAP instruction). INTM can also be set to
1 by a hardware reset or by execution of a disable-interrupts instruction
(SETC INTM). You can clear INTM by executing the enable-interrupts
instruction (CLRC INTM). INTM has no effect on reset, NMI, or software-
interrupts (initiated with the TRAP, NMI, and INTR instructions). Also,
INTM is unaffected by the LST (load status register) instruction.

INTM does not modify the interrupt flag register (IFR), the interrupt mask
register (IMR), or the interrupt control register (ICR).

When the CPU acknowledges a maskable hardware interrupt, it loads the
instruction bus with the INTR instruction. This instruction forces the CPU to
branch to the corresponding

interrupt vector location. From this location in pro-

gram memory, the CPU fetches a branch that leads to the appropriate interrupt
service routine. As the CPU branches to the interrupt service routine, it also
sets the INTM bit to 1, preventing all hardware-initiated maskable interrupts
from interrupting the execution of the ISR. Note that the INTR instruction can
also be initiated directly by software; thus, the interrupt service routines for the
maskable interrupts can also be initiated directly with the INTR instruction (see
subsection 5.6.7,

Nonmaskable Interrupts on page 5-27).

To determine which vector address has been assigned to each of the inter-
rupts, see subsection 5.6.2 (on page 5-16). Interrupt vector locations are
spaced apart by two addresses so a 2-word branch instruction can be accom-
modated in each of the locations.