Texas Instruments TMS320C2XX - Manual (Page 573)

Index
Index-10
IMR (interrupt mask register) 5-22 to 5-38
bits
’C203/C204 5-23
’C209 11-13
in interrupt acknowledgement process 5-19
quick reference A-7
IN instruction 7-69
IN0 bit 9-10
indirect addressing
description 6-9
effects on auxiliary register pointer
(ARP) 6-14 to 6-16
effects on current auxiliary register 6-14 to 6-16
examples 6-15
modifying auxiliary register content 6-17
opcode format 6-12 to 6-14
operands 6-10
operation types 6-14 to 6-16
options 6-9
possible opcodes 6-14 to 6-16
input clock modes
’C203/C204 8-5
’C209 11-14
input scaling section of CPU 3-3
input shifter 3-3
input/output space. See I/O space
input/output status register (IOSR)
description 10-10
detecting change on pins IO0–IO3 10-16
reading current logic level on pins
IO0–IO3 10-16
instruction register (IR), definition F-11
instruction set, key features 1-7
instructions 7-1 to 7-20
Boolean logic
AND 7-34
CMPL (complement/NOT) 7-64
OR 7-129
XOR (exclusive OR) 7-193
compared with those of other TMS320 de-
vices B-1 to B-36
conditional 5-10 to 5-13
branch (BCND) 7-43
call (CC) 7-60
conditions that may be tested 5-10
return (RETC) 7-143
stabilization of conditions 5-11
using multiple conditions 5-10
instructions (continued)
CPU halt until hardware interrupt (IDLE) 7-68
delay/no operation (NOP) 7-125
descriptions 7-20
how to use 7-12
enhanced B-5
idle until hardware interrupt (IDLE) 7-68
interrupt
branch to NMI interrupt vector location
(NMI) 7-124
branch to specified interrupt vector location
(INTR) 7-71
branch to TRAP interrupt vector location
(TRAP) 7-192
negate accumulator (NEG) 7-122
no operation (NOP) 7-125
normalize (NORM) 7-126
OR 7-129
power down until hardware interrupt
(IDLE) 7-68
repeat next instruction n times
description (RPT) 7-146
introduction 5-14
stack
pop top of stack to data memory
(POPD) 7-137
pop top of stack to low accumulator bits
(POP) 7-135
push data memory value onto stack
(PSHD) 7-139
push low accumulator bits onto stack
(PUSH) 7-141
status registers ST0 and ST1
clear control bit (CLRC) 7-62
load (LST) 7-87
load data page pointer (LDP) 7-83
modify auxiliary register pointer (MAR) 7-111
set control bit (SETC) 7-155
set product shift mode (SPM) 7-167
store (SST) 7-172
summary 7-2 to 7-11
test bit specified by TREG (BITT) 7-47
test specified bit (BIT) 7-45
INT1 bit (’C209)
in interrupt flag register (IFR) 11-12
in interrupt mask register (IMR) 11-13