Texas Instruments TMS320C2XX User Manual
Page 238
Load Product Register High Word
LPH
7-85
Assembly Language Instructions
Syntax
LPH
dma
Direct addressing
LPH
ind [, ARn]
Indirect addressing
Operands
dma:
7 LSBs of the data-memory address
n:
Value from 0 to 7 designating the next auxiliary register
ind:
Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
LPH
dma
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
1
0
dma
LPH
ind [, ARn]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
1
1
ARU
N
NAR
Note:
ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode (page 6-9).
Execution
Increment PC, then ...
(data-memory address)
→
PREG (31:16)
Status Bits
None
Description
The 16 high-order bits of the PREG are loaded with the content of the specified
data-memory address. The low-order PREG bits are unaffected.
The LPH instruction can be used for restoring the high-order bits of the PREG
after interrupts and subroutine calls.
Words
1
Cycles for a Single LPH Instruction
Program
Operand
ROM
DARAM
SARAM
External
DARAM
1
1
1
1+p
SARAM
1
1
1, 2
†
1+p
External
1+d
1+d
1+d
2+d+p
† If the operand and the code are in the same SARAM block
Opcode
Cycles