Texas Instruments TMS320C2XX - Manual (Page 572)

Index
Index-9
H
hardware interrupts
definition 5-15
nonmaskable external 5-27
priorities 5-16
types 5-15
hardware reset 5-33
header
14-pin E-2
dimensions, 14-pin E-2
HOLD (HOLD operation request pin)
definition 4-4
use in HOLD operation 4-27
HOLD acknowledge pin (HOLDA)
definition 4-4
use in HOLD operation 4-27
HOLD operation
description 4-27
during reset 4-29
example 4-28
terminating correctly 4-29
HOLD operation request pin (HOLD)
definition 4-4
use in HOLD operation 4-27
HOLD/INT1 bit
in interrupt flag register (IFR) 5-22
in interrupt mask register (IMR) 5-24
HOLD/INT1 interrupt
flag bit 5-22
mask bit 5-24
priority 5-16
vector location 5-16
HOLD/INT1 pin, mode set by MODE bit 5-24
HOLDA (HOLD acknowledge pin)
definition 4-4
use in HOLD operation 4-27
I
I/O
general-purpose pins
input
BIO 8-17 to 8-18
IO0–IO3 10-15 to 10-16
output
IO0–IO3 10-15 to 10-16
XF 8-18
I/O (continued)
parallel ports 4-25
serial ports
asynchronous 10-1 to 10-20
introduction 2-12
synchronous 9-1 to 9-30
I/O space
accessing 4-25
address map 4-23
caution about reserved addresses 4-24
description 4-23
external interfacing 4-25
instructions
transfer data from data memory to I/O space
(OUT) 7-132
transfer data from I/O space to data memory
(IN) 7-69
on-chip registers mapped to
’C203/C204 4-24
’C209 11-9
accessing 4-25
pins for external interfacing 4-3
I/O space select pin (IS)
definition 4-3
shown in figure 4-26
I/O status register (IOSR)
description 10-10
detecting change on pins IO0–IO3 10-16
quick reference A-14
reading current logic level on pins
IO0–IO3 10-16
I/O-mapped registers, addresses and reset val-
ues A-2
IACK signal 11-13
ICR (interrupt control register) 5-24 to 5-38
bits 5-26
quick reference A-8
IDLE instruction 7-68
IEEE 1149.1 specification, bus slave device
rules E-4
IFR (interrupt flag register) 5-20 to 5-38
bits
’C203/C204 5-21
’C209 11-12
clearing interrupts 5-20
quick reference A-6
immediate addressing 6-2