Texas Instruments TMS320C2XX User Manual
Page 571
Index
Index-8
emulator
cable pod
connection to target system, JTAG mechanical
dimensions
designing the JTAG cable
emulation pins
pod interface
pod timings
signal buffering
target cable, header design
enhanced instructions
error conditions
asynchronous serial port
framing error (FE bit)
overrun (OE bit)
synchronous serial port
burst mode
continuous mode
examples of ’C2xx program code
external access active strobe (STRB)
external address bus (A0–A15)
definition
shown in figure
external data bus (D0–D15)
definition
shown in figure
external device ready pin (READY)
definition
generating wait states with
external interfacing, diagrams
external oscillator, using (diagram)
F
FE bit
features summary
FIFO buffers, introduction
FINT2 bit
FINT3 bit
flag bits
I/O status register (IOSR)
interrupt control register (ICR)
interrupt flag register (IFR)
flash memory (on-chip), introduction
flow charts
interrupt operation
maskable interrupts
nonmaskable interrupts
requesting INT2 and INT3
TMS320 ROM code submittal
4-level pipeline operation
14-pin connector, dimensions
14-pin header
header signals
JTAG
FR1 and FR0 bits
frame synchronization mode (FSM bit)
framing error (FE bit)
FREE bit
asynchronous serial port
synchronous serial port
timer
FSM bit
FSR pin
FSX pin
FT1 and FT0 bits
G
general-purpose I/O pins
input
BIO
IO0–IO3
output
IO0–IO3
XF
generating executable files, figure
generating wait states with
generators (on-chip)
baud-rate generator
clock generator
’C209 clock options
11-14 to 11-18
wait-state generator
’C209
11-16 to 11-18
global data memory
configuration
external interfacing
global memory allocation register (GREG)
GREG (global memory allocation register)