Texas Instruments TMS320C2XX - Manual (Page 530)

Emulation Design Considerations
E-18
E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL)
Example E–3 and Example E–4 help you to calculate the key emulation tim-
ings in the SPL secondary scan path of your system. For actual target timing
parameters, see the appropriate device data sheet for your target device.
The examples use the following assumptions:
t
su(TTMS)
Setup time, target TMS/TDI to TCK high 10 ns
t
d(TTDO)
Delay time, target TDO from TCK low 15 ns
t
d(bufmax)
Delay time, target buffer, maximum 10 ns
t
d(bufmin)
Delay time, target buffer, minimum 1 ns
t
(bufskew)
Skew time, target buffer, between two
devices in the same package:
[t
d(bufmax)
– t
d(bufmin)
]
×
0.15
1.35 ns
t
(TCKfactor)
Duty cycle, TCK assume a 40/60% clock 0.4
(40%)
Also, the examples use the following values from the SPL data sheet:
t
d(DTMSmax)
Delay time, SPL DTMS/DTDO from TCK
low, maximum 31 ns
t
su(DTDLmin)
Setup time, DTDI to SPL TCK high,
minimum 7 ns
t
d(DTCKHmin)
Delay time, SPL DTCK from TCK high,
minimum 2 ns
t
d(DTCKLmax)
Delay time, SPL DTCK from TCK low,
maximum 16 ns
There are two key timing paths to consider in the emulation design:
- The TCK-to-DTMS/DTDO path, called t
pd(TCK-DTMS)
- The TCK-to-DTDI path, called t
pd(TCK-DTDI)