beautypg.com

Control of on-chip peripherals, 1 control of on-chip peripherals – Texas Instruments TMS320C2XX User Manual

Page 352

background image

Control of On-Chip Peripherals

8-2

8.1

Control of On-Chip Peripherals

The on-chip peripherals are controlled by accessing control registers that are
mapped to on-chip I/O space. Data is also transferred to and from the peripher-
als through these registers. Setting and clearing bits in these registers can en-
able, disable, initialize, and dynamically reconfigure the on-chip peripherals.

On a device reset, the CPU sends an internal SRESET signal to the peripheral
circuits. Table 8–1 lists the peripheral registers and summarizes what hap-
pens when the values in these registers are reset. For a description of all the
effects of a device reset, see Section 5.7,

Reset Operation, on page 5-33.

Table 8–1. Peripheral Register Locations and Reset Conditions

Register

I/O Address

Register
Name

’C209

Other ’C2xx

Reset Value

Effects at Reset

CLK

FFE8h

0000h

CLKOUT1-pin control (CLK) register. The
CLKOUT1 signal is available at the
CLKOUT1 pin.

SDTR

FFF0h

xxxxh

Synchronous data transmit and receive
register. The value in this register is unde-
fined after reset.

SSPCR

FFF1h

0030h

Synchronous serial port control register.
The port emulation mode is set to immedi-
ate stop. Error and status flags are reset.
Receive interrupts are set to occur when the
receive buffer is not empty. Transmit inter-
rupts are set to occur when the transmit
buffer can accept one or more words. Exter-
nal clock and frame synchronization
sources are selected. Continuous mode is
selected. Digital loopback mode is disabled.
The receiver and transmitter are enabled.

ADTR

FFF4h

xxxxh

Asynchronous data transmit and receive
register. The value in this register is unde-
fined after reset.

ASPCR

FFF5h

0000h

Asynchronous serial port control register.
The port emulation mode is set to immedi-
ate stop. Receive, transmit, and delta in-
terrupts are disabled. One stop bit is se-
lected. Auto-baud alignment is disabled.
The TX pin is forced high between trans-
missions. I/O pins IO0, IO1, IO2, and IO3
are configured as inputs. The port is
disabled.