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Mpya – Texas Instruments TMS320C2XX User Manual

Page 269

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MPYA

Multiply and Accumulate Previous Product

7-116

Syntax

MPYA

dma

Direct addressing

MPYA

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

n:

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–

MPYA

dma

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

0

1

0

0

0

0

0

dma

MPYA

ind [, ARn]

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

0

1

0

0

0

0

1

ARU

N

NAR

Note:

ARU, N, and NAR are defined in Section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...
(ACC) + shifted (PREG)

ACC

(TREG)

×

(data-memory address)

PREG

Status Bits

Affected by

Affects

PM and OVM

C and OV

Description

The contents of TREG are multiplied by the contents of the addressed data
memory location. The result is placed in the product register (PREG). The pre-
vious product, shifted as defined by the PM status bits, is also added to the
accumulator.

Words

1

Cycles for a Single MPYA Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1

1

1

1+p

SARAM

1

1

1, 2

1+p

External

1+d

1+d

1+d

2+d+p

† If the operand and the code are in the same SARAM block

Opcode

Cycles