Texas Instruments TMS320C2XX - Manual (Page 158)

Instruction Set Summary
7-5 Assembly Language Instructions
Table 7–1. Accumulator, Arithmetic, and Logic Instructions (Continued)
Mnemonic Opcode Cycles Words Description
AND AND ACC with data value, direct or indirect 1 1 0110 1110 IAAA AAAA
AND with ACC with shift of 0 to 15, long immediate 2 2 1011 1111 1011 SHFT
+ 1 word
AND with ACC with shift of 16, long immediate 2 2 1011 1110 1000 0001
+ 1 word
CMPL Complement ACC 1 1 1011 1110 0000 0001
LACC Load ACC with shift of 0 to 15, direct or indirect 1 1 0001 SHFT IAAA AAAA
Load ACC with shift of 0 to 15, long immediate 2 2 1011 1111 1000 SHFT
+ 1 word
Load ACC with shift of 16, direct or indirect 1 1 0110 1010 IAAA AAAA
LACL Load low word of ACC, direct or indirect 1 1 0110 1001 IAAA AAAA
Load low word of ACC, short immediate 1 1 1011 1001 IIII IIII
LACT Load ACC with shift (0 to 15) specified by TREG,
direct or indirect 1 1 0110 1011 IAAA AAAA
NEG Negate ACC 1 1 1011 1110 0000 0010
NORM Normalize the contents of ACC, indirect 1 1 1010 0000 IAAA AAAA
OR OR ACC with data value, direct or indirect 1 1 0110 1101 IAAA AAAA
OR with ACC with shift of 0 to 15, long immediate 2 2 1011 1111 1100 SHFT
+ 1 word
OR with ACC with shift of 16, long immediate 2 2 1011 1110 1000 0010
+ 1 word
ROL Rotate ACC left 1 1 1011 1110 0000 1100
ROR Rotate ACC right 1 1 1011 1110 0000 1101
SACH Store high ACC with shift of 0 to 7,
direct or indirect 1 1 1001 1SHF IAAA AAAA
SACL Store low ACC with shift of 0 to 7,
direct or indirect 1 1 1001 0SHF IAAA AAAA
SFL Shift ACC left 1 1 1011 1110 0000 1001
SFR Shift ACC right 1 1 1011 1110 0000 1010