Texas Instruments TMS320C2XX User Manual
Page 576
Index
Index-13
LACC instruction
LACL instruction
LACT instruction
LAR instruction
latch phase of CPU cycle
latency, interrupt
after execution of RET
during execution of CLRC INTM
minimum latency
LDP instruction
local data memory
address map
’C203
’C204
’C209
11-6
configuration
RAM (dual-access)
’C203
’C204
’C209
RAM (single-access)
11-7
description
external interfacing
caution about proper timing
pages of (diagram)
logic instructions
AND
CMPL (complement/NOT)
OR
XOR (exclusive OR)
logic phase of CPU cycle
long immediate addressing
LPH instruction
LST instruction
LT instruction
LTA instruction
LTD instruction
LTP instruction
LTS instruction
M
MAC instruction
MACD instruction
MAR instruction
mask bits
asynchronous serial port control register
(ASPCR)
interrupt control register (ICR)
interrupt mask register (IMR)
maskable interrupts
acknowledgement conditions
definition
enabling/disabling with INTM bit
flag bits in ICR
flag bits in IFR
flow chart of operation
flow chart of requesting INT2 and INT3
masking/unmasking in ICR
masking/unmasking in IMR
MCM bit
memory
See also I/O space
address map
’C203
’C204
’C209
11-6
data page 0
available on TMS320C2xx devices
available types
boot loader
boot source (EPROM)
diagram
enabling
execution
generating code for EPROM
program code
data page pointer (DP)
device-specific information
direct memory access (using HOLD opera-
tion)
during reset
example
terminating correctly
external interfacing
global data memory
I/O ports
local data memory
program memory
flash, introduction
global data memory
HOLD operation
during reset
example
terminating correctly