Texas Instruments TMS320C2XX User Manual
Page 582

Index
Index-19
registers
(continued)
mapped to data page 0
mapped to I/O space
’C203/C204
’C209
11-9
accessing
quick reference
status registers ST0 and ST1
timer
control register (TCR)
’C203/C204
’C209
counter register (TIM)
divide-down register (TDDR)
’C203/C204
’C209
period register (PRD)
prescaler counter (PSC)
’C203/C204
’C209
wait-state generator control register (WSGR)
’C203/C204
’C209
11-17
repeat (RPT) instruction
description
introduction
repeat counter (RPTC)
repeating a single instruction
reset
at same time as HOLD operation
effects
introduction
priority
’C203/C204
’C209
11-10
vector location
’C203/C204
’C209
11-10
reset values of on-chip registers
mapped to data space
mapped to I/O space
status registers ST0 and ST1, A-2
RET instruction
RETC instruction
return instructions
conditional, overview
return conditionally from subroutine
(RETC)
return unconditionally from subroutine
(RET)
unconditional, overview
RFNE bit
RIM bit
RINT bit
in interrupt flag register (IFR)
in interrupt mask register (IMR)
RINT interrupt
definition
flag bit
mask bit
priority
vector location
ROL instruction
ROM, customized
ROM (on-chip)
configuration
’C204
’C209
11-7
introduction
ROM codes, submitting to Texas Instru-
ments
ROR instruction
RPT instruction
RPTC (repeat counter), 5-14
RRST bit
RS (reset)
at same time as HOLD operation
effects
introduction
priority
’C203/C204
’C209
11-10
vector location
’C203/C204
’C209
11-10
RSR (synchronous serial port receive shift regis-
ter)
run/stop operation
RUNB, debugger command
RUNB_ENABLE, input
RX pin