Texas Instruments TMS320C2XX User Manual
Page 581

Index
Index-18
program memory
(continued)
configuration
RAM (dual-access)
’C203
’C204
’C209
RAM (single-access)
11-7
ROM
’C204
’C209
description
external interfacing
caution about proper timing
program memory select pin (PS)
definition
shown in figure
program read bus (PRDB)
program-address generation (diagram)
protocol, bus, in emulator system
PS (program memory select pin)
definition
shown in figure
PSC (timer prescaler counter)
’C203/C204
’C209
definition
PSHD instruction
PSLWS bits
PSUWS bits
PSWS bit
PUSH instruction
push operation (diagram)
R
R/W (read/write pin)
RAM (on-chip)
dual-access
configuration
’C203
’C204
’C209
description
single-access
configuration
11-7
description
RAMEN (single-access RAM enable pin)
definition
use in configuring memory
RD (read select pin)
definition
shown in figure
read select pin (RD)
definition
shown in figure
read/write pin (R/W)
READY (external device ready pin)
definition
generating wait states with
receive interrupt
asynchronous serial port
enabling/disabling (RIM bit)
synchronous serial port
receive pin
asynchronous serial port (RX)
detecting break on (BI bit)
synchronous serial port (DR)
receive register
asynchronous serial port (ADTR)
detecting overrun in (OE bit)
detecting when empty (DR bit)
synchronous serial port (SDTR)
receive shift register
asynchronous serial port (ARSR)
synchronous serial port (RSR)
register summary
registers
addresses and reset values
asynchronous serial port
baud-rate divisor register (BRD)
control register (ASPCR)
I/O status register (IOSR)
receive shift register (ARSR)
transmit shift register (AXSR)
auxiliary registers, current auxiliary regis-
ter
auxiliary registers (AR0–AR7)
current auxiliary register
next auxiliary register
baud-rate divisor register (BRD)
CLKOUT1-pin control (CLK) register
I/O status register (IOSR)
interrupt control register (ICR)
interrupt flag register (IFR)
’C209
11-12 to 11-18
interrupt mask register (IMR)
’C209
11-13 to 11-18