Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 222)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65N) 222
6.4.20 LED Status and Control Register
The following table provides a detailed description about LED Status and Control Register.
Table 6-73 LED Status and Control Register
Address Offset: 0x50
Bit Description Default Access
0 Control green LED output Signal LED_GREEN_:
0: LED_GREEN_ is driven high.
1: LED_GREEN_ is driven low. 0 LPC: r/w
IPMC: r
1 Control read LED output Signal LED_RED_:
0: LED_RED_ is driven high.
1: LED_RED_ is driven low. 0 LPC: r/w
IPMC: r
2 Control user LED output Signal LED_USER1_:
0: LED_USER1_ is driven high.
1: LED_USER1 is driven low. 0 LPC: r/w
IPMC: r
3 Control user LED output Signal LED_USER2_:
0: LED_USER2_ is driven high.
1: LED_USER2 is driven low. 0 LPC: r/w
IPMC: r
5:4 Reserved 0 r
6 Signal level of ME_DISABLE_ (Connected to SW1.4
and ICH10 GP33) Ext. r
7 FPGA PROM select signal FPGA_PROM_SEL
controlled by IPMC
Ext.
r