Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 125)

BIOS
ATCA-7365 Installation and Use (6806800K65N) 125
It is recommended to test the application which will run on the blade with different CPU
settings in order to select the best configuration.
4.7 Memory Configuration
The Intel Xeon processor 5600 series supports four different memory RAS (Reliability,
Availability, and Serviceability) Modes: Independent Channel Mode, Spare Channel Mode,
Mirrored Channel Mode, and Lockstep Channel Mode.
4.7.1 Independent Channel Mode
In Independent mode, all three channels are operating independently. The ECC code appears
in each independent channel. Failure of the DRAM can be corrected. The correction capabilities
in Independent mode are:
 Correction of any x4 DRAM device failure.
 Detection of 99.986% of all single bit failures that occur in addition to an x4 DRAM failure.
 Detection of any 2-bit uncorrectable errors.
4.7.2 Spare Channel Mode
In Spare Channel Mode, Channel 0 and 1 are active channels and Channel 2 is the spare of the
other two channels. The spare channel is held in reserve and is not available as system memory.
The spare channel must have identical population to the channel being copied from. This
means that all three channels must have identical population with regards to size and
organization. The Memory Controller will maintain correctable ECC error counters for each
DIMM in the system that can either trigger an SMI event or be periodically polled by software
to determine whether a high error rate is happening. SMI Software can then configure the
Integrated Memory Controller to copy contents from one channel to another.
4.7.3 Mirrored Channel Mode
The Integrated Memory Controller supports mirroring across channels. DIMM organization in
each slot of one channel must be identical to the DIMM in the corresponding slot of the other
channel. When mirroring is enabled, the memory image in Channel 0 is maintained similar to
Channel 1. DIMMs in Channel 2 are unused.